A microprocessor manufacturing company has $3$ CPU chips that implement the same ISA:

C$1$: uses a single$-$cycle Datapath and runs @ $1GHz$

C$2$: uses multi$-$cycle Datapath and runs @ $4$GHz $($the number of CPI varies from $3$ to $5$ cycles per

instruction with an avg $\frac{C}{P}$I $=4)$

C$3$: uses an ideal $5-$stage pipeline and runs @ $4$GHz

Give concise and short answers to the following questions:

a$)$ What is the throughput for each of the chips $($C$1,$ C$2$ and C$3)?$

b$)$ How long does it take to execute a $2000$ instruction program on the CPU chips:

C$1$

C$2($given that it has $600$ instructions with $3$ CPI, $1200$ instructions of $4$ CPI and $200$ instructions of $5$ CPI$)$

C$3($assume an ideal pipeline$)$