A multicore system contains two $(2)$ RISC V processors, P$1$ and P$2.$ Each processor maintains a private data cache employing a write$-$back update scheme with the MESI snooping protocol $($as shown in Fig. $1)$ to maintain coherence.

MESI$\_$v$1.$png

Figure $1.$ State transition diagram for the MESI protocol.

Processors P$1$ and P$2$ execute a sequence of memory access operations on a shared memory address in the following order $($the address is stored in register a$0$ on both P$1$ and P$2)$:

a$0$: $0$x$123$

P$1$: lw t$0,0($a$0)$

P$1$: sw t$0,0($a$0)$

P$2$: lw t$1,0($a$0)$

P$2$: sw t$1,0($a$0)$

P$1$: lw t$0,0($a$0)$

P$1$: sw t$0,0($a$0)$

Using the tabular format shown below, list the shared bus transactions $($Bus Read, Bus Read Ex$,$ Bus Write or Shared$)$ and the state $($Modified$,$ Exclusive, Shared or Invalid$)$ of the cache entry for Mem$[$a$0]$ in the cache for both P$1$ and P$2$ after each instruction. If no shared bus transaction is issued, enter $$None$.$

Operation P$1$ Bus Transaction P$2$ Bus Transaction P$1$ Cache State P$2$ Cache State

Initial state $$ Invalid Invalid

P$1$: lw t$0,0($a$0)$

P$1$: sw t$0,0($a$0)$

P$2$: lw t$1,0($a$0)$

P$2$: sw t$1,0($a$0)$

P$1$: lw t$0,0($a$0)$

P$1$: sw t$0,0($a$0)$