| A pipelined CPU must address the issue of dealing with branches. Branch dependencies reduce the...

 

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| A pipelined CPU must address the issue of dealing with branches. Branch dependencies reduce the overall execution rate. In RISC machines, the "delayed branch" strategy is commonly used to optimise branching. Using the strategy to improve performance, code reorganization techniques have been developed so that the execution order of instructions can be re-arranged without changing the original semantics of the program. Consider the following instructions in Figure 3. MOV # 5. R00 SUB #1, R00 JUMP SSTORE ADD R00, R01 STORE: HLT Figure 3 3.2) To simulate the "delayed branch" strategy, re-arrange the instructions in Figure 3 accordingly to improve the total time required (i.e. improving total clock cycles). Run the re-arranged instructions and print screen the Instruction Pipeline result window. [2 marks] Answer: 3.3) Explain briefly the improvement made by the re-arrangement of the instructions in question 3.2. [2 marks] | A pipelined CPU must address the issue of dealing with branches. Branch dependencies reduce the overall execution rate. In RISC machines, the "delayed branch" strategy is commonly used to optimise branching. Using the strategy to improve performance, code reorganization techniques have been developed so that the execution order of instructions can be re-arranged without changing the original semantics of the program. Consider the following instructions in Figure 3. MOV # 5. R00 SUB #1, R00 JUMP SSTORE ADD R00, R01 STORE: HLT Figure 3 3.2) To simulate the "delayed branch" strategy, re-arrange the instructions in Figure 3 accordingly to improve the total time required (i.e. improving total clock cycles). Run the re-arranged instructions and print screen the Instruction Pipeline result window. [2 marks] Answer: 3.3) Explain briefly the improvement made by the re-arrangement of the instructions in question 3.2. [2 marks]

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