Question: A pipelined processor is executing the following instruction sequence: 1 . LOAD R 2 , 0 ( R 1 ) 2 . LOAD R 4
A pipelined processor is executing the following instruction sequence:
LOAD RR
LOAD RR
SUB R R R
ADD R R R
The processor has two configurations:
With forwarding: Data is forwarded as soon as it's available
Without forwarding: Instructions dependent on results on results from previous instructions must stall until the result is written back
Assume:
Each instruction completes in cycles without stalls.
Data hazards only occur for readafterwrite RAW dependencies.
a With forwarding enabled, fill in the blanks below:
Instruction completes in cycle
Instruction completes in cycle
Instruction completes in cycle
Instruction completes in cycle
b Without forwarding, calculate the total number of stall cycles needed to handle data hazards
Instruction requires stall cycles
Instruction requires stall cycles
Instruction requires stall cycles
Instruction requires stall cycles
Total stall cycles
c Total cycles: calculate the total number of cycles for the entire sequence with and without forwarding
With forwarding : cycles
Without forwarding: cycles
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