A register file has 16 registers each having 16 bits. The registers RF[0] to RF[15] contain...

   

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A register file has 16 registers each having 16 bits. The registers RF[0] to RF[15] contain positive or negative integers. Design an HLSM which will find the sum of absolute values of the 16 integers stored in RF[0] to RF[15]. The negative numbers are in 2's complement form. The sum is going to be stored in a separate SUM register. Upon reset, the HLSM will be in the initial state waiting for the GO signal. When the operation is completed the HLSM will return to its initial state and wait for a GO signal to start over again. Show your design clearly. (a) Capture the system behavior as an HLSM and draw the state transition diagram. (b) Design the datapath for this HLSM. Specify each component in the datapath clearly (i.e. name of the component, input signals, output signals, number of bits, etc.). (c) Connect the datapath to the controller (FSM) and show the signals between the controller and the datapath. (d) Derive the FSM and draw the state transition diagram. A register file has 16 registers each having 16 bits. The registers RF[0] to RF[15] contain positive or negative integers. Design an HLSM which will find the sum of absolute values of the 16 integers stored in RF[0] to RF[15]. The negative numbers are in 2's complement form. The sum is going to be stored in a separate SUM register. Upon reset, the HLSM will be in the initial state waiting for the GO signal. When the operation is completed the HLSM will return to its initial state and wait for a GO signal to start over again. Show your design clearly. (a) Capture the system behavior as an HLSM and draw the state transition diagram. (b) Design the datapath for this HLSM. Specify each component in the datapath clearly (i.e. name of the component, input signals, output signals, number of bits, etc.). (c) Connect the datapath to the controller (FSM) and show the signals between the controller and the datapath. (d) Derive the FSM and draw the state transition diagram.

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Designing an HLSM Hardwired Logic State Machine involves several steps Given the complexity of your ... View the full answer