a$.$ RISC architectures typically do not include a dedicated $$INC$($increment$)$

instruction $($e$.$g$.,$ inc dst$,$ which adds $1$ to the destination register$).(1)$ Why might

such an instruction be excluded from a RISC ISA? $(2)$ List three alternative

instructions or instruction sequences that achieve the same effect as an INC

instruction. $(10$pt$)$