A RISC processor is implemented in two versions of synchronous organization: a unicycle, where each instruction executes in exactly one clock cycle, and a 5-stage pipeline version. The stages of the pipeline version are: (1) search instruction, (2) search for operands, (3) execution of the operation, (4) access to memory and (5) updating of the register database. The maximum operating frequency of the organizations was calculated in 100 MHz for the unicycle version and 400 MHz for the pipeline version. An X program that executes 200 statements is used to compare the performance of organizations. Of the 200 instructions, only 40% access memory, while the others operate only on the organization's internal registers. Assume that the program does not present any data or control conflicts between statements that may be simultaneously within the pipeline of the second organization. Thus, the execution time of program X in the unicycle and pipeline organizations is, respectively:

Choose one: A. 2,000 nanoseconds and 500 nanoseconds B. 2,000 nanoseconds and 510 nanoseconds C. 2,000 nanoseconds and 2,300 nanoseconds D. 2,300 nanoseconds and 510 nanoseconds E. 2,300 nanoseconds and 500 nanoseconds