Question: A single-cycle processor has a cycle-time, T = 5 ns and processes one instruction every cycle, CPI = 1.0. All basic device timing parameters are

 A single-cycle processor has a cycle-time, T = 5 ns andprocesses one instruction every cycle, CPI = 1.0. All basic device timing

A single-cycle processor has a cycle-time, T = 5 ns and processes one instruction every cycle, CPI = 1.0. All basic device timing parameters are given on the front page. We wish to pipeline this processor. 1 The throughput is defined, PA. (measured with units IPS) (CPI)t You MUST show algebraic expressions for all calculations before substituting numbers. (-ve score warning) Let N = the number of pipeline stages. Let At = cycle time for the pipelined processor. Let O = the per stage timing overhead. a) Calculate the unpipelined throughput in units of MIPS. b) State an expression for the pipelined cycle time. Do not substitute values. c) Derive an expression for the pipelined throughput. Do not substitute values. Assume that cache penalties cause interruptions with a penalty of (N-1) cycles and occur at a rate C. branch instruction hazards cause interruptions with a penalty of N/2 cycles and occur at a rate B. d) Derive an expression for the optimal number of pipeline stages. Sample e) Given 0 = 1 ns, C = 20% and B = 10%, calculate a numerical bound on the number of pipeline stages. A single-cycle processor has a cycle-time, T = 5 ns and processes one instruction every cycle, CPI = 1.0. All basic device timing parameters are given on the front page. We wish to pipeline this processor. 1 The throughput is defined, PA. (measured with units IPS) (CPI)t You MUST show algebraic expressions for all calculations before substituting numbers. (-ve score warning) Let N = the number of pipeline stages. Let At = cycle time for the pipelined processor. Let O = the per stage timing overhead. a) Calculate the unpipelined throughput in units of MIPS. b) State an expression for the pipelined cycle time. Do not substitute values. c) Derive an expression for the pipelined throughput. Do not substitute values. Assume that cache penalties cause interruptions with a penalty of (N-1) cycles and occur at a rate C. branch instruction hazards cause interruptions with a penalty of N/2 cycles and occur at a rate B. d) Derive an expression for the optimal number of pipeline stages. Sample e) Given 0 = 1 ns, C = 20% and B = 10%, calculate a numerical bound on the number of pipeline stages

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