A state machine has two inputs named a and $b,$ a reset input named reset, and a clock input named clk$.$ It has no outputs. The state transition diagram is shown below. Write a Verilog module named quad that implements this state machine. Use the state encodings shown in the diagram. Include the module declaration and any additional required signal declarations. NO CHAT GPT OR ANY AI PLEASE, I WANT HAND WRITTEN SOLUTION. THANK YOU