A technician was asked to design a digital clock with seconds minutes and hour digituses using $4-$bit binary counters with a block diagram and operating mode below. However, the technician who can design the seconds and minute digit thought that the clock digit should be a MOD $24$ BCD AMR counter, but could not design it$.$ You have been asked for help CLK with the design of the watch digital. Can you help the UP CO CLR technician design the watch digital?

EN is the enable input. If it is the most active, the counter mode, and if it is passive, the counter works in the defined changes status. LD$,$ on the other hand, is the parallel upload input, which is the priority input. UP logic counts down if it is zero $(0)$ and up if it is one $(1).$ CO normally drops to logic $1,$ and when counter outputs are $1111,$ it drops to logic $0.$Only drawing a block$/$circuit diagram is not enough. Properly explain how you designed the circuit