a$.$ The verilog code at right models a $3-$to$-8$ decoder with enable and activehigh outputs. However, it has a functional bug, which prevents it from behaving as intended. Explain what the bug is and provide the simplest possible code fix. $(10$ pts$)$

always @$(*)$ begin

if $($E$)$ begin

$Y[A]=1\text{'}b1$;

end else begin

Y $=8\text{'}$b$0000\_0000$;

end end

endmodule

b$.$ The above dec$3$to$8$ module is used to control a traffic light consisting of three lights: $R(ed),Y(ellow),G(reen).$ The truth tables for R$,$ Y$,$ and G are given at right. Draw the block diagram of this traffic light decoder consisting of a dec$3$to$8$ logic block and some gates. $(5$ pts$)$

$\backslash$table$[[A_2{A}_1{A}_0,R,Y,G$