A true data dependency is said to exist when an instruction writes a register that is required as an input by a following instruction. An anti$-$dependency occurs if an instruction overwrites a register that is required as an input by an earlier instruction. If two or more instructions write a result to the same register, the register writes must be performed in the correct order; this is called an output dependency.$$ One of the three terms $($WAR$,$ WAW or RAW$)$ can be used as an alternate name for each of these three types of dependencies.

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Consider the following instruction sequence containing instructions that execute on a superscalar system allowing out of order instruction execution.$$

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$1.$ lui$$ $$6,0$x$4000$

$2.$ lw$$ $$4,8($$$6)$

$3.$ add$$ $$5,$ $$0,$ $$0$

$4.$ addiu$$ $$4,$ $$5,4$

$5.$ sw$$ $$5,8($$$6)$

$6.$ sll$$ $$5,$ $$5,2$

$7.$ addiu$$ $$6,$ $$6,8$

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Complete the table below by filling in the blank entries to identify the register involved in each possible data dependency, the type of data dependency $($WAR$,$ WAW or RAW$),$ the two instructions involved in the dependency and whether register renaming can eliminate the dependency.$$ For each instruction that makes use of a renamed register, show the complete instruction with the new register name substituted. Choose the next higher unused register name for the next register that is renamed. For example: $$7,$ $$8,$ $$9,$ $$10,$ etc. can be used to rename registers where needed.

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Minimum clock rate required for the $5-$stage scalar pipeline $=\_\_\_\_\_\_\_\_\_\_\_$

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b$)(5)$ After the superpipeline fills, what is the minimum number of nanoseconds required to complete $12$ independent R$-$type instructions on a degree$-8$ superpipelined system running at a clock rate of $1$ GHz$?$

Register

$($WAR$,$ WAW or RAW$)$

First instruction

Second instruction

Reg. renaming works? $($yes or no$)$

Instruction with renamed register

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