a$)$ Using the ASM chart as reference, design the Register Transfer Level $($RTL$)$ model of the bit counter in Verilog.

b$)$ If an asynchronous reset signal were to be included in the bit counter to reset register B to zero and register A to its initial value, what changes would you make to the RTL model in part $($a$)?$

Refer to the following Algorithmic State Machine $($ASM$)$ chart in FIGURE Q$1.$