a$)$ What is a test vector that triggers the bug?

b$)$ Briefly describe how you found this test vector.

c$)$ List some alternative ways you could have found a test vector to trigger the bug.

d$)$ Consider a $16-$bit adder. The fast SystemVerilog simulator on my office computer takes $1\mathrm{.}5$ minutes to apply

$224$ test vectors. Assuming constant time per test vector, how long would it take to exhaustively simulate the

$16-$bit adder? If we further assume the same constant time per test vector for a $32-$bit adder, how long would an

exhaustive test take?