accordingly. Note that since the two numbers have been sorted, the magnitude of max is always

larger than that of min and the final sign is the sign of max

Design the circuit as follows:

Develop a Verilog program that meets the specified requirements.

Create a testbench for this program. Simulate it and verify that the design functions

correctly.

Write a top$-$level Verilog program to implement and test the design on an FPGA board.

Universal binary counter program

A universal binary counter is more versatile. It can count up or down, pause, be loaded with a

specific value, or be synchronously cleared. Its functions are summarized in Table below. Note

the difference between the reset and syn$\_$clr signals. The former is asynchronous and should only

be used for system initialization. The latter is sampled at the rising edge of the clock and can be

used in normal synchronous design.

Table $5\mathrm{.}1$ Function table of a universal binary counter

Develop a Verilog program that meets the specified requirements.

Create a testbench for this program. Simulate it and verify that the design functions

correctly.

Write a top$-$level Verilog program to implement and test the design on an FPGA board.

Heartbeat Program

We want to create a "heartbeat" for the prototyping board. It repeats the simple pattern in the

four$-$digit seven$-$segment display, as shown in Figure $5\mathrm{.}14,$ at a rate of $72$ Hz $($change to $1$ Hz for

demonstration purpose$).$ Design the circuit and verify its operation on the prototyping board.

Develop a Verilog program that meets the specified requirements.