Adapted from $5\mathrm{.}19\mathrm{.}3$ You don't need to answer $($b$)$ to answer $($c$),$ but in case you are

interested, the answer for $($c$)$ is $549,376$ bits.

By convention, a cache is named according to the amount of data it contains $($i$.$e$.,$ a $4$ KiB cache

can hold $4$ KiB of data$)$; however, caches also require SRAM to store metadata such as tags and

valid bits. For this exercise, you will examine how a cache's configuration affects the total

amount of SRAM needed to implement it as well as the performance of the cache. For all parts,

assume that the caches are byte addressable, and that addresses and words are $64$ bits.

$($a$)$ Calculate the total number of bits required to implement a $32$ KiB cache with two$-$word

blocks.

$($c$)$ Explain why this $64$ KiB cache, despite its larger data size, might provide slower

performance than the first cache.