Add logic and data paths to the single cycle LC$-3$ implementation to allow for the following instructions:

a$.$ BR

b$.$ JMP

c$.$ JSR

d$.$ JSRR

e$.$ RET For each of the instructions, explain in words how the data flows through the data path.

Assume the following timing data for the various components used in the single cycle and pipelined implementations of the LC$-3$

Element Delay $($ps$)$ Register clock to Q $30$ Register setup $20$ Multiplexer $2\mathrm{.}5$ ALU$/$Adder $200$ Memory read or write $250$ Sign$/$zero extension $1$ Register file read $150$ Register file setup $20$

For the single cycle implementation shown below, what is the maximum clock speed that can be obtained?

For the pipelined implementation below, what is the minimum clock cycle time required for each

stage, namely:

a$)$ Data fetch stage

b$)$ Data decode stage

c$)$ Register read stage

d$)$ ALU operation stage

e$)$ Memory read$/$write stage

f$)$ Register writeback stage

What's the max clock speed for this pipelined implementation?

If you could reduce the delay for one component, which would you choose? How much would you

reduce the delay? $($hint: at some point, reducing the delay in one component doesn't help reduce the

clock period$)$

If you could speed up two componenets, which two? How much would you reduce their delays?

LC$3$ Pipelined Implementation

Please use the included diagram and element delay timing chart in your answer please. Thank you so much!