Question: additional control logic is required in the pipeline to forward the value of register RZ shown in the figure. WHat specific conditions must this additional

additional control logic is required in the pipeline to forward the value of register RZ shown in the figure. WHat specific conditions must this additional logic check to determine the settings of the multiplexers feeding the ALU inputs in the Compute stage of the pipeline?

Figure link: http://i.imgur.com/nMFZ6k5.jpg

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