Question: Address bus 11 10 9 CPU RD WR 8-1 Data bus Decoder 3 2 1 0 RAM 1 RD WR AD RD WR AD RAM

Address bus 11 10 9 CPU RD WR 8-1 Data bus

Address bus 11 10 9 CPU RD WR 8-1 Data bus Decoder 3 2 1 0 RAM 1 RD WR AD RD WR AD RAM 2 RAM 3 RD WR AD Data RD WR AD RAM 4 CS1 CS2 ROM AD a- Study the above diagram and answer the following questions. How many words available on each ROM Chip? b- How many words available on each RAM Chip? Complete the following address map table. C- Component Hex address Address Bus 11 10 9 8 7 6 5 4 3 2 1 RAM1 X X X X IX X X RAM2 X X X X X X X RAM3 IX X X X X X X RAM4 X X X X X X X ROM 0 X X X X X X X

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