After this activity, you will be able to

Design a circuit to generate the instruction sequencing signals using analytical digital design techniques, and

Verify that the implementation you specify satisfies the requirements

Problem Statement

For this learning activity, you are required to design a circuit to generate the instruction sequencing signals used to ensure the proper sequencing of the control signals generation for instruction fetch and execute, which will effectively complete your control unit design.

The circuit is a Finite State Machine $($FSM$)$ with $3$ inputs $($that is$,$ the $3-$bit opcode$)$ and $8$ possible states. Because there are $8$ possible states, the circuit requires $3$ sequential elements to store the current state. The figure below describes the state transition behavior.$$

The circuit must also generate a signal to indicate when an instruction is being fetched and when it is being executed. During timing pulses T$0-$T$3,$ Execute $=0,$ indicating the instruction is being fetched. For any remaining timing pulses for a given instruction, Execute $=1,$ indicating the execution of the current instruction.$$

Here is the entity statement:$$

ENTITY instruction$\_$sequencer IS$$

$$ PORT

$($

$$ opcode : in std$\_$logic$\_$vector$(2$ downto $0)$;

$$ reset : in std$\_$logic;

$$ clock : in std$\_$logic;

$$ t$0$ : out std$\_$logic;

$$ t$1$ : out std$\_$logic;

$$ t$2$ : out std$\_$logic;

$$ t$3$ : out std$\_$logic;

$$ t$4$ : out std$\_$logic;

$$ t$5$ : out std$\_$logic;

$$ t$6$ : out std$\_$logic;

$$ t$7$ : out std$\_$logic;

$$ execute : out std$\_$logic

$)$;

END instruction$\_$sequencer;

You must use this entity statement. Your instruction$\_$sequencer design should use three D flip flops and combinational logic. You may use the D flip flop given here: d$\_$ff$.$vhd Download d$\_$ff$.$vhd$.$ Outside of the given d$\_$ff component, you cannot use if statements, case statements, or other higher$-$level programming constructs in your design; you are welcome to use these in your testbench if you so chose. please do this in vhdl $($also testbench$)$