Aim of this mini project is to develop a logic for the $4$ directional $($East$/$West$/$North$/$South$)$ traffic

light controller

Specification

To develop Traffic light controller logic which can control the traffic on the $4$ directional road.

Features

Controls four traffic signals at a four$-$way crossing.

The traffic light cycle: Red $=>$ Yellow $=>$ Green $=>$ Yellow $=>$ Red.

Transition from Red to Green is always through Yellow.

Ensures only one signal is green at a time.

Green$-$light duration: $5$ seconds.

Yellow light duration: $1$ second.

Operates in a clockwise direction of traffic signals.

The hardware resets at all Yellow so the reset is safe and will not cause any confusion.

The output is encoded as follows to get $8-$bit output

$R=00$

$Y=01$

$G=10$

Current state next state output BIN

RSt s$0$ YYYY $01010101$

s$0$ s$1$ GRRR $10000000$

s$1$ s$2$ YYRR $01010000$

s$2$ s$3$ RGRR $00100000$

s$3$ s$4$ RYRR $00010000$

s$4$ s$5$ RRGR $00001000$

s$5$ s$6$ RRYY $00000101$

S$6$ s$7$ RRRG $00000010$

s$7$ s$8$ YRRY $01000001$

write a verilog code for this design specifications