Al$-$Balqa Applied University

Problem # $2$: In a single$-$core, single$-$threaded $1GHz$ processor that executes instructions using a simple four$-$stage pipeline, as shown in the figure below, each unit performs its work for an instruction in one clock. To keep things simple, assume this is the case for all instructions in the program, including loads and stores $($memory is infinitely fast$).$ The figure shows the execution of a program with six independent instructions on this processor.

However, if instruction $B$ depends on the results of instruction $A,$ instruction $B$ will not begin the IF phase of execution until the clock after WB completes for A$.[6$pts$]$

A$-$Assuming all instructions in a program are independent $($yes$,$ a bit unrealistic$)$ what is the instruction throughput of the processor? $[2$pts$]$

B$-$ Assuming all instructions in a program are dependent on the previous instruction, what is the instruction throughput of the processor? $[2$pts$]$

C$-$ What is the latency $($in $ns)$ of completing an instruction? $[2$pts$]$