Question: All problems here assume 3 2 - bit memory address as in the case of MIPS. A cache with a single block of 6 4
All problems here assume bit memory address as in the case of MIPS. A cache with a single block of Bytes is used with v and tag x How many bits are used for tag? answer in decimal, such as How many bits are used for inblock offset? answer in decimal, such as When accessing memory address x this should access which block in memory? answer in decimal, such as The tag part of this address is answer in hex, such as acx Is this access a hit? yn
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