$.$

ALL

Shown below is a flop inside an SPI device. In its device specification sheet, setup time for the data capture inside it must be marked on its ports. Assume below values

buffer delay of $0\mathrm{.}025$ns $($min$)$ and $0\mathrm{.}05$ns $($max$),$

each net segment delay is $0\mathrm{.}02$ns

Setup time of flop is $0\mathrm{.}1$ns and hold time is $0\mathrm{.}05$ns

rise$/$fall delays to be equal.