ALSO NOTE THAT CDigits $$E$$ and $$F$$ are expected to act as $$C$($clear$)$ and $+$ inputs for the calculator, respectively. The

following behavior is expected:

Key Sequence Display

$--------------------$

C $00000000$

$100000001$

$3,600000136$

$+00000136$

$4,500000045$

$+00000181$

$700000007$

$+00000188$

C $00000000$

$3,300000033$

$+00000033$

$1,100000011$

$+00000044$

C $00000000$

Important notes:

$$ Each of registers X and Y should contain $4\backslash$times $8=32$ bits.

$$ Full synchronous design: all FFs to be driven with the clock signal, and no clock gating

$$ Fully schematic design. HDL code is not accepted.

$$ Work in groups.

At the assigned deadline, return all $.$dig files of your design.