Among the following VHDL code snippets, which ones comply with VHDL restrictions?

Select one:

a$.$

ARCHITBCrURE architecture$\_$name of entity$\_$name Is

BEGIN

Declerations$\_$for$\_$architecture;

code:

BND architecture$\_$nane;

b$.$

AnCHITBCTUIE architecture$\_$type OF enticy$\_$name IS

BEGIN

Declarations$\_$for$\_$architecture;

code;

END architecture$\_$type;

c$.$ none of all

d$.$

ARCHITBCTURE architecture$\_$name OP entity$\_$name IS

Declarations$\_$for$\_$archicec$$cure;

BEGIN

Code:

BND architecture$\_$name:

e$.$

ARCHITECTURE architecture$\_$nare OY entity$\_$name IS

Declarations$\_$for$\_$architecture

BEGIN

code:

END architecture$\_$name;