An I$/$O module generates data for transfer to a CPU at an average rate of $200$KBsec $$on a continuous basis. The device is connected to a DMA module that transfers characters directly to

main memory using cycle stealing. It takes one clock cycle to transfer one byte of data from the DMA module to the memory. The processor executes instructions at the rate of $16$million

instructions per second $(16$MIPS$).$

Suppose each instruction takes two clock cycles to execute. In the first cycle of each instruction, the CPU fetches the instruction from memory, and in the second cycle, it fetches an

operand from main memory to a CPU register. There are no other data fetches or stores. By how much is the processor slowed down due to the DMA activity? Express your answer as a

percentage.

Now suppose that each instruction takes four clock cycles to execute. In the first cycle, the CPU fetches the instruction from memory; in the second cycle, it fetches an operand from

memory; in the third cycle, it executes the operation, which involves no memory access; and in the fourth cycle, it stores the result of the operation into a location in main memory.

Suppose the cycle stolen by the DMA device randomly falls during one of the four cycles of instruction execution. In this case, by how much is the processor slowed down due to the

DMA activity? As before, express your answer as a percentage.