answer for number 1 is provided, need help with number 2.

compare:

addi $sp, $sp, 4

sw $ra, 0($sp)

add $s0, $a0, $0

add $s1, $a1, $0

jal sub

addi $t1, $0, 1

beq $v0, $0, exit

slt $t2, $0, $v0

bne $t2, $0, exit

addi $t1, $0, $0

exit:

add $v0, $t1, $0

lw $ra, 0($sp)

addi $sp, $sp, 4

jr $ra

sub:

sub $v0, $a0, $a1

jr $ra

1) Rewrite the following delayed branch MIPS snippet to maximize performance, assuming it has forwarding. addi $v0, $v0, 1 addi $tl, ?a0, 4 lw $t0, 0 ($tl) add $a0, $t0, ?al addi $a0, $a0, 4 bne $to, $0, Loop nop jr $ra Loop: 2) Now, assume for the delayed branch code from above exercise that our hardware can execute Static Dual Issue for any two instructions at once. Using reordering (with nops for padding), but no loop unrolling, schedule the instructions to make the loop take as few clock cycles as possible. 1) Rewrite the following delayed branch MIPS snippet to maximize performance, assuming it has forwarding. addi $v0, $v0, 1 addi $tl, ?a0, 4 lw $t0, 0 ($tl) add $a0, $t0, ?al addi $a0, $a0, 4 bne $to, $0, Loop nop jr $ra Loop: 2) Now, assume for the delayed branch code from above exercise that our hardware can execute Static Dual Issue for any two instructions at once. Using reordering (with nops for padding), but no loop unrolling, schedule the instructions to make the loop take as few clock cycles as possible