answer nd explain accordingly

1.what is the generator for the low impedance path in the Latch-up effect?

2.falsify;To reduce latch-up effect substrate resistance should be high.

3.what is the effect of reduction of beta/alpha in the reduction in carrier lifetime

4. he parasitic PNP transistor has the effect of _______ carrier lifetime.

5.what element should the BJT gain to avoid the latch-up effect

6.provide the contributing factor to the catch up element in Sudden transient in power

7.how is thepositive feedback connect with f BJTs

8.elaborate with facts the main factor for reducing the latch-up effect?make sure you base onreduced n-well resistance

9.how is the vulnerability tolatch-up effect initiated by BiCMOS?

10..demonstrarwe the role of guard rings in reducing latch-up effect after introduction

reference

Yilmaz, H. (2015). Cell geometry effect on IGT latch-up.IEEE electron device letters,6(8), 419-4201