Answer only q4 i asked quesiton 3 in another post, you can answer q3 on that post

Q4 For the question 3, try to calculate a possible hit ratio for the main loop in your answer. Assume that the cache memory fetches from the main memory in 128-bit long blocks (16 bytes). Calculate the hit ratio only for data accesses, not for instruction fetches. Q3 Design an assembly program that computes the Fibonacci Series. Each element of this series can be computed by adding previous two elements. Your design will be for 32-bit Intel Architecture, and each element will be 32- bit integer. You can explain the initialization part by your own words, and give only the assembly listing for the main loop. (Fibonacci Series: 0,1,1,2,3,5,8,13,21, ...)