Answer the cirlced questions please

$(1.)$ Draw a logic diagram constructing a $38$ decoder with active$-$low enable, using a pair of $24$ decoders; also draw a truth table for the configuration.

$2.$ Write Verilog code that is equivalent to the logic of a $24$ decoder, be sure to include wires and an enable$-$bit. Name the module decoder$\_2$x$4\_$gates.

$3.$ Write Verilog code that uses Procedural Assignment Statements. A procedural assignment statement executes a process once at the beginning of simulation; thereafter, its sensitivity list determines when the association begins. The end block statement will then execute, said statement executes when a signal in its sensitivity list changes. For example, the statements associated with the sensitivity list @ $($clock$)$ will start executing when clock has an event. $[$Bonus$]$

$4.$ Construct a $416$ decoder with five $24$ decoders with an enable$-$bit.

$5.$ Using a decoder and external gates, design the combinational circuit defined by the following three Boolean functions:

$F_1=x^{\text{'}}z+xz$

$F_2=yz+x{y}^{\text{'}}+y^{\text{'}}{z}^{\text{'}}$

$F_3=x^{\text{'}}{z}^{\text{'}}+y^{\text{'}}{z}^{\text{'}}$