Answer the following questions based on the following table. All different datapaths support the following four instruction types with listed delay of each component. Assume no hazard is detected in the pipelined datapath. Explain your answer

a) What should clock cycle time be for the single-cycle and pipelined datapaths? Explain your answer.

b) What is the latency (defined as the delay from when the instruction enters the datapath until it finishes) of an R-format instruction in the single-cycle and pipelined datapaths?

c) What is the latency (defined as the delay from when the instruction enters the datapath until it finishes) of load word (lw) instruction in the single-cycle and pipelined datapaths?

d) What is the averaged throughput (defined as the number of instructions executed in 1 nanosecond in this case) of the single-cycle and pipelined datapaths? Assume the frequency of four different instruction types are the same.
 

Instruction Register fetch Register Total write ALU Data Instruction class read operation access time Load word (1 w) 100 ps 200 ps 100 ps 800 ps 200 ps 200 ps 200 ps Store word (sw) 100 ps 200 ps 200 ps 700 ps R-format (add, sub, and, or, slt) 200 ps 100 ps 200 ps 100 ps 600 ps Branch (beq) 200 ps 100 ps 200 ps 500 ps