Answer with good high level explanation please, can you clarify how the $200$ MHz clock rate is used in generating the answers to each of the three questions?

Consider three different MIPS systems each of which runs at a $200MHz$ clock rate.

Each system employs one or more $5-$stage instruction pipelines. In cycle $1$ all three

systems start fetching and executing a stream of instructions. One of the systems is a

scalar system, another is a degree$-4$ super pipelined system and the third is a degree$-4$

superscalar system. Superscalar and superpipelined systems were defined and described

in module $8.$ Assume the same instruction sequence containing only independent R$-$type

instructions is executed by each of the three systems.

a$)$ By the end of clock cycle $10,$ what is the maximum number of the instructions the

scalar system can complete?

b$)$ By the end of clock cycle $10,$ what is the maximum number of instructions the degree$-$

$4$ superpipelined system can complete?

c$)$ By the end of clock cycle $10,$ what is the maximum number of instructions the degree$-$

$4$ superscalar system can complete?