Question: Architectural simulation is widely used in computer architecture studies because it allows us to estimate the performance impact of new designs. In this part of

Architectural simulation is widely used in computer architecture studies because it allows us to estimate the performance impact of new designs. In this part of the project, you are asked to add a new branch predictor implementation to SimpleScalar. It has already implemented 2-bit branch history table (called bimod in the simulator), correlating predictor (called 2lev) and several others. The 2-bit branch history table uses the 2-bit saturating counter that we have discussed in the class. You are asked to implement another 2-bit branch history table that uses the 2-bit counter as shown in the textbook, Figure C.15. You need to make changes to bpred.h and bpred.c of SimpleScalar to implement the new 2-bit counter and also a small change to sim-outorder.c to add a new choice of branch predictor types. Next, you can run the simulation and report the observed results. What is the impact on both the overall performance and branch prediction accuracy when using the two different implementations of 2-bit counters? Compared with the perfect branch predictor that is implemented by SimpleScalar, how much is the performance loss due to branch mis-predictions for these two 2-bit branch predictors? Similar to the experiments in Project Part 1, please use the option -fastfwd 1000000000 to fastforward the first 1000 million instructions and collect statistics on the next 500 million instructions (using the option -max:inst 500000000) for the program sjeng (sjeng reduced.txt). Please include your experimental results and source code (the parts that have been modified) in your report (including the screenshots of timestamps, statistics and the changes to bpred.c in your report).
Figure C.15 The states in a 2-bit prediction scheme. By using 2 bits rather than 1, a branch that strongly favors taken or not taken-as many branches do-will be mispredicted less often than with a 1-bit predictor. The 2 bits are used to encode the four states in the system. The 2-bit scheme is actually a specialization of a more general scheme that has an \( n \)-bit saturating counter for each entry in the prediction buffer. With an \( n \)-bit counter, the counter can take on values between 0 and \(2^{n}-1\) : when the counter is greater than or equal to one-half of its maximum value \(\left(2^{n}-1\right)\), the branch is predicted as taken; otherwise, it is predicted as untaken. Studies of \( n \)-bit predictors have shown that the 2-bit predictors do almost as well, thus most systems rely on 2-bit branch predictors rather than the more general \( n \)-bit predictors.
Architectural simulation is widely used in

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