Architicture - Tomasulo's algorithm question

Here is the table 3.4:

And here is the details in page 98

A. Fill in the cycles an instruction spends in each stage (per Table 3.4 and details on p. 98), showing the start and end cycles in each column. Initially, all registers are logical and the ROB is empty. Show the assigned reservation station, ROB entry, reasons for delays, if any, in the "Explanations" column. Decken Disp IS Ex Comm Explanations Instr. F3 F2 F1 1/1 2/2 F1