Are the following statements true?

$(30$ points; $+1,0,-1$ point per statement$)$

Statements

In mansers transformation.

A machine code instruction specifies what is the given operation and where are the operands.

RAM memory can be considered as a matrix of bit cells.

The names of the three terminals of a transistor are anode, cathode, and ground.

There is no traffic on the address bus from the memory to the processor.

In the case of CISC$-$based processors, only the Load and Store data transfer instructions access the memory, the other instructions work with registers.

In a processor, the clock signal is used to define the logical low and high voltage levels.

Peripheral devices can be accessed through the I$/$O interfaces.

Context save is not necessary for non$-$maskable interrupts.

PATA and PCI are parallel bus systems.

The writeback cache distinguishes "dirty" and "clean" lines.

peculative execution is used by the processor during stochastic modeling.

risk management technique called register renaming allows the programmer to

stomize the processor's instruction set architecture.

hen applying the pipeline bubble $($stall$),$ the execution of instructions is delayed oiding hazards.

$2$

The pipeline operation is impossible in GPU.

The instruction execution speed of a processor is inver yes no of its clock signal.

frequency

$\backslash$table$[[$ncy$.,$yes,no$],[,$yes,no$],[,$yes,no$],[$nmunicate with each other.,yes,no$]]$

What do you know about pipeline hazards? $($Meaning$,$ types, treatment methods, etc.$)$ Write some sentences about them.

$15$ points

Are the following statements true?

$(30$ points; $+1,0,-1$ point per statement$)$

Statements

In mansers transformation.

A machine code instruction specifies what is the given operation and where are the operands.

RAM memory can be considered as a matrix of bit cells.

The names of the three terminals of a transistor are anode, cathode, and ground.

There is no traffic on the address bus from the memory to the processor.

In the case of CISC$-$based processors, only the Load and Store data transfer instructions access the memory, the other instructions work with registers.

In a processor, the clock signal is used to define the logical low and high voltage levels.

Peripheral devices can be accessed through the I$/$O interfaces.

Context save is not necessary for non$-$maskable interrupts.

PATA and PCI are parallel bus systems.

The writeback cache distinguishes "dirty" and "clean" lines.

peculative execution is used by the processor during stochastic modeling.

risk management technique called register renaming allows the programmer to

stomize the processor's instruction set architecture.

hen applying the pipeline bubble $($stall$),$ the execution of instructions is delayed oiding hazards.

$2$