As an Electrical Engineer, you have been asked to design a receiver that detects a particular sequence of
bits transmitted from a remote transmitter. Your system is a MOORE machine that has an input ‘w’ and
an output ‘z’ that produces z=1 when the previous two values of w are 00 or 11 otherwise it should give
z=0;
Please keep in mind that designing includes
1. State Diagram
2. State Table
3. State Reductions and optimized state table
4. State Equations
5. Implementation using D-Flip flops
6. Verilog Implementation (Code and output/test-bench) 

Answer rating: 100% (QA)

and the verilog code for the FSM module MOOREVerilogwclockresety input clock clock signa... View the full answer