As shown below, the two memory outputs $($TRAN$\_$out, DIRE$\_$out$)0$ are output for two clock cycles, and then the x output is output for seven cycles before the desired output comes out. Please let me know we have to modify in the top module or in the stimulus file so that the desired output comes out immediately$($without $0$ unlike i uploaded.$)($out$\_$mat has to come out with TRAN$\_$out and DIRE$\_$out at the same time$)$ Assume that the modules instantiated in the top module are well defined.

module top$\_$FIR$\_$filter $($input clk$,$ rstn$,$

input signed $[14-1$:$0]$ C$0,$ C$1,$ C$2,$ C$3,$ C$4,$ C$5$

$)$;

wire signed $[16-1$:$0]$ X$\_$direct, X$\_$transpose;

wire signed $[26-1$:$0]$ Y$\_$direct, Y$\_$transpose;

reg NCE$\_$in$,$ NCE$\_$out;

wire NWRT$\_$in$,$ NWRT$\_$out;

reg $[8-1$:$0]$ ADDR$\_$in$,$ ADDR$\_$out;

reg $[3-1$:$0]$ state$\_$count;

assign NWRT$\_$in $=1\text{'}$b$1$; $//$read

assign NWRT$\_$out $=1\text{'}$b$0$; $//$write

always @ $($posedge clk or negedge rstn$)$

begin

if$(!$rstn$)$

begin

ADDR$\_$in b$0$;

ADDR$\_$out b$0$;

NCE$\_$in b$1$;

NCE$\_$out b$1$;

end

else

begin

ADDR$\_$in ADDR$\_$in$+1\text{'}$b$1$;

ADDR$\_$out ADDR$\_$out$+1\text{'}$b$1$;

NCE$\_$in b$0$;

NCE$\_$out b$0$;

end

end

$//$Memory for direct FIR filter

rflp$256$x$16$mx$2$ DIRECT$\_$INPUT$\_$MEM $(.$NWRT$($NWRT$\_$in$),.$DIN$(),.$RA$($ADDR$\_$in$[7$:$2]),.$CA$($ADDR$\_$in$[1$:$0]),.$NCE$($NCE$\_$in$),.$CLK$($clk$),.$DO$($X$\_$direct$))$;

FIR$\_$filter$\_$direct DIRECT$\_$FIR $(.$clk$($clk$),.$rstn$($rstn$),.$X$($X$\_$direct$),.$C$0($C$0),.$C$1($C$1),.$C$2($C$2),.$C$3($C$3),.$C$4($C$4),.$C$5($C$5),.$Y$($Y$\_$direct$))$;

rflp$256$x$26$mx$2$ DIRECT$\_$OUTPUT$\_$MEM $(.$NWRT$($NWRT$\_$out$),.$DIN$($Y$\_$direct$),.$RA$($ADDR$\_$out$[7$:$2]),.$CA$($ADDR$\_$out$[1$:$0]),.$NCE$($NCE$\_$out$),.$CLK$($clk$),.$DO$())$;

$//$Memory for transpose FIR filter

rflp$256$x$16$mx$2$ TRANS$\_$INPUT$\_$MEM $(.$NWRT$($NWRT$\_$in$),.$DIN$(),.$RA$($ADDR$\_$in$[7$:$2]),.$CA$($ADDR$\_$in$[1$:$0]),.$NCE$($NCE$\_$in$),.$CLK$($clk$),.$DO$($X$\_$transpose$))$;

FIR$\_$filter$\_$transpose TRANS$\_$FIR $(.$clk$($clk$),.$rstn$($rstn$),.$X$($X$\_$transpose$),.$C$0($C$0),.$C$1($C$1),.$C$2($C$2),.$C$3($C$3),.$C$4($C$4),.$C$5($C$5),.$Y$($Y$\_$transpose$))$;

rflp$256$x$26$mx$2$ TRANS$\_$OUTPUT$\_$MEM $(.$NWRT$($NWRT$\_$out$),.$DIN$($Y$\_$transpose$),.$RA$($ADDR$\_$out$[7$:$2]),.$CA$($ADDR$\_$out$[1$:$0]),.$NCE$($NCE$\_$out$),.$CLK$($clk$),.$DO$())$;

endmodule

$`$timescale $1$ns$/10$ps

module sti$\_$FIR$\_$filter;

reg clk$,$ reset;

reg $[25$:$0]$ sig$\_$mat $[0$:$255]$;

reg $[25$:$0]$ out$\_$mat;

reg $[25$:$0]$ TRAN$\_$out;

reg $[25$:$0]$ DIRE$\_$out;

wire $[13$:$0]$ c$0=14\text{'}$h$3$aa$4$ ;

wire $[13$:$0]$ c$1=14\text{'}$h$1433$;

wire $[13$:$0]$ c$2=14\text{'}$he$37$;

wire $[13$:$0]$ c$3=14\text{'}$h$1$a$57$;

wire $[13$:$0]$ c$4=14\text{'}$h$917$;

wire $[13$:$0]$ c$5=14\text{'}$h$2$c$1$d;

top$\_$FIR$\_$filter FIR$($clk$,$ reset, c$0,$ c$1,$ c$2,$ c$3,$ c$4,$ c$5)$;

integer err$=0$;

initial

begin

clk $=1$;

reset $=0$;

#$10$

reset $=1$;

end

always #$5$ clk $=$ ~clk;

initial $readmemh$("$input$\_$vector$\_$hex.txt$",$ FIR.DIRECT$\_$INPUT$\_$MEM.array$)$; $//$check the path of memory rocation $($module instance$)$

initial $readmemh$("$input$\_$vector$\_$hex.txt$",$ FIR.TRANS$\_$INPUT$\_$MEM.array$)$; $//$check the path of memory rocation $($module instance$)$

integer i$=0$;

initial

begin

$readmemh$("$output$\_$vector$\_$hex.txt$",$ sig$\_$mat$)$;

#$(140)$;

for $($i$=0$; i$<mn>2</mn><mn>5</mn><mn>6</mn>$; i$=$i$+1)$

begin

out$\_$mat sig$\_$mat$[$i$]$;

TRAN$\_$out $=$ FIR.DIRECT$\_$OUTPUT$\_$MEM.array$[$i$]$;

DIRE$\_$out $=$ FIR.TRANS$\_$OUTPUT$\_$MEM.array$[$i$]$;

if$(($TRAN$\_$out $!=$ out$\_$mat$)||($DIRE$\_$out $!=$ out$\_$mat$))$ err $=$ err $+1$;

#$(10)$;

end

$stop;

end

endmoduleL.