ashboard / My courses / ADVANCED DIGITAL SY Question 3 Verilog is case sensitive only ir Not yet answered Select one: Marked out of 1.00 O a. Variables P Flag question O b. System primitives O c. Verilog key words O d. All of the options O e. Module names Previous page Jecture link Time left 1 estion 4 yet In memory, the access time is not always equal to the cycle time. wered Select one: rked out of O True Flag question O False estion 7 The test bench is the smallest building block in Verilog otyet swered Select one: arked out of Do O True O False Flag question Time left 1:23:45 Question 8 What is the total memory size reserved in the following instruction? reg [7: O] memram [0: 8192]; Not yet answered Marked out of 1.00 P Flag question Select one: O a. None of the given O b. 16 Kbyte O c. 4 Kbyte O d. 16 MByte o e. 8 Mbyte Question 9 How many argument bits are required to implement the case statement if you have 4 options? Not yet answered Marked out of 1.00 Select one: O a. 2 P Flag question O b. 3 O c. 8 O d. only begin and end are needed O e. 1 ADVANCED DIGITAL SYSTEM 20201_110813220 AAUP - JE ashboard / My courses / ADVANCED DIGITAL SYSTEMS DESIGN Question 10 In Verilog, A UDP may model one output. Not yet answered Select one: ws Marked out of 1.00 O True Flag question O False Previous page Lecture Link password 123 Jump to