Assembly language /MIPS

outer scence puter science 270 final May 17, 2018 Question 2. (30 points) Caches are important to providing high performance memory hierarchy to processors. Below is a list of 32-bit memory address references in decimal, given as byte addresses. 3, 180, 43, 2, 191, 88, 190, 14, 181,44, 186, 253 You are asked to optimize a cache design for the given references. There are three direct- mapped cache designs possible, all with a total of 8 words of data: C1 has 1-word blocks C2 has 2-word blocks C3 has 4-word blocks (15 points) In terms of miss rate, which cache design is the best ? Please show your work. (15 points) If the miss stall time is 25 cycles, and C1 has an access time of 2 cycles, C2 takes 3 cycles, and C3 takes 5 cycles, which is the best cache design? Please show your work