Assembly Language Program Help. I need help coming up with the rest of the code.

CECS 225 Fall 2017 Digital Logic and Assembly Programming LAB 4 Sequential Logic Due: Friday, October 6th, 2017 10 Points OBJECTIVE: Create a D-FlipFlop, a 1-bit storage element. PROCEDURE: In this lab, model a 1-bit storage element known as the D FlipFlop. The Logic circuit is given below P1 n1 Clock- P2 n5 na n2 Each of the logic gates in the circuit above are nand gates Note the cyclic paths that exist in the circuit. This is the characteristic of sequential logic i.c. a circuit that has memory. The next output that will be produced also depends on the previous output that was produced. Use the given Verilog skeleton code on the next page to get started: Lab 1 Page 1 of 3 CECS 225 Fall 2017 Digital Logic and Assembly Programming LAB 4 Sequential Logic Due: Friday, October 6th, 2017 10 Points OBJECTIVE: Create a D-FlipFlop, a 1-bit storage element. PROCEDURE: In this lab, model a 1-bit storage element known as the D FlipFlop. The Logic circuit is given below P1 n1 Clock- P2 n5 na n2 Each of the logic gates in the circuit above are nand gates Note the cyclic paths that exist in the circuit. This is the characteristic of sequential logic i.c. a circuit that has memory. The next output that will be produced also depends on the previous output that was produced. Use the given Verilog skeleton code on the next page to get started: Lab 1 Page 1 of 3