Assembly Language

The general Fibonacci sequence is a sequence that starts with f0=0 and f1=1 . The next number in the sequence is the sum of previous two numbers. So the Fibonacci number sequence generated in our circuit will be: 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89 Here is the circuit you may use. Please make an effort to understand the working of this circuit and explain it as comments in your HDL file. To use this circuit, you have to control these signals, namely, enable1, enable2, enable3 and msel. msel=0 will select the starting values f0 and f1 of the Fibonacci Sequence msel=1 will keep running the Fibonacci sequence with sum(t+1) sum(t) + sum(t-1) for clock cycle t enable1=1 or enable2=1 or enable3=1 activate respective registers by loading the corresponding input values to corresponding register outputs enable1=0 or enable2=0 or enable3=0 retain the register outputs from the previous cycle The test file Fibonacci.tst assigns the values to these control signals. See how output in the Fibonacci.out file changes while changing those signals.

base code:

CHIP Fibonacci {

IN f0[16], enable1, msel, enable2, enable3, f1[16];

OUT out[16];

PARTS:

//Put your code here