Assignment 2 - A Simple ALU Description Page 2 o ALU Figure 1: Simple ALU Figure 1 above shows the structural description of an ALU. The ALU is made up of two components (3x8 Decoder and Arithmetic & Logic Module) which are interconnected by signal wires. The ALU accepts two 8-bit signal buses, operand1 and operand2, and a 3-bit opcode signal bus and output one 8-bit signal ALU_RESULT as shown. (Note: the input and output of the decoder may be treated as a 3 bit and 8 bit bus respectively) (a) Give the entity declaration of the ALU. b A component must be declared before it can be used. Give the VHDL declaration of each component within the ALU (c) Give the VHDL architecture of the top level module. Assignment 2 - A Simple ALU Description Page 2 o ALU Figure 1: Simple ALU Figure 1 above shows the structural description of an ALU. The ALU is made up of two components (3x8 Decoder and Arithmetic & Logic Module) which are interconnected by signal wires. The ALU accepts two 8-bit signal buses, operand1 and operand2, and a 3-bit opcode signal bus and output one 8-bit signal ALU_RESULT as shown. (Note: the input and output of the decoder may be treated as a 3 bit and 8 bit bus respectively) (a) Give the entity declaration of the ALU. b A component must be declared before it can be used. Give the VHDL declaration of each component within the ALU (c) Give the VHDL architecture of the top level module