Assignment Objectives

This assignment will help you practice working with bit vectors, bitwise operations, conditional logic, and behavioral modeling of combinational logic circuits in Verilog. In particular, you are required to identify the position of the least significant $\text{'}1\text{'}$ bit in the input vector and manipulate the bits accordingly to produce the desired output efficiently.

Main Assignment Questions and Requirements

Design and implement a combinational logic circuit in Verilog that processes an $8-$bit binary input $D=D[7$:$0]$ and produces an $8-$bit output $S=S[7$:$0]$ based on the following specifications:

Complementation Rule: Identify the position of the least significant $\text{'}1\text{'}$ bit in the input vector $D.$ Complement all bits to the right of this position. The bits at and to the left of the least significant $\text{'}1\text{'}$ bit should remain unchanged in the output $S.$

Zero Input Condition: If the input $D$ is all zeros $($i$.$e$.,D=8^{\text{'}}$ b$0000\_0000),$ the output $S$ should be identical to the input.

Examples

The table below illustrates how the input $D$ is mapped into the output $S$ :

$\backslash$table$[[$Input $D,$Least Significant $\text{'}1\text{'}$ Position,Output S$],[8\text{'}$b$1011\_0000,$Bit $4($D$[4]),8\text{'}$b$1011\_1111],[8\text{'}$b$0000\_0010,$Bit $1($D$[1]),8\text{'}$b$0000\_0011],[8\text{'}$b$0000\_0000,$N$/$A$,8\text{'}$b$0000\_0000]]$

$1$

Assignment

Module Implementation:

Create a Verilog module named top with the following port declaration:

Input: D $(8-$bit vector$)$

Output: S $(8-$bit vector$)$

The module should implement the logic as per the specifications mentioned earlier.

Design Requirements:

Ensure your design is efficient and uses the minimal amount of logic necessary.

You may use any combinational logic constructs introduced so far, including bitwise operations and conditional statements.

Starter Code

Below is the skeleton code for the top.v module. Complete the module by adding your implementation where indicated