Assume a computer system that uses $32-$bit, byte$-$accessible, memory addresses. For each of the following three

cache configurations, provide a cache design table $($showing how the address bits are used$)$ and memory access

table $($showing hits and misses$)$ for the following memory access sequence with addresses given in decimal:

Memory Addresses $($in decimal$)$:

$32,34,49,48,256,512,32,40,256,512$

Cache Design:

Memory Access:

Configuration $1-$ Assume the configuration is a direct$-$mapped cache of $16$ four$-$word blocks and that the

cache starts empty. What is the hit ratio?

Configuration $2-$ Assume the configuration is a three$-$way set associative cache of $24$ one$-$word blocks with

a LRU replacement policy, and that the cache starts empty. In this cache, there are $24$ one$-$word blocks total,

so each of the $3$ sets has $8$ blocks each. What is the hit ratio?

Configuration $3-$ Assume the configuration is a fully associative cache of $16$ two$-$word blocks with a LRU

replacement policy, and the cache starts empty. What is the hit ratio?