Assume a standard pipelined RISC$-$V processor implementation with no data forwarding that has three functional

units: a single cycle adder, a single cycle shifter, and a two cycle multiplier. The IF stage, ID stage and WB stage, are

all single cycle. Note that there is no MEM stage.

Also assume that an instruction sequence with the following characteristics is made to run on it:

$10-$ needs two execute cycles $($a multiply$)$

$11-$ any data independent instruction with no structural hazard

$12-$ any data independent instruction with no structural hazard

$13-$ needs the same function unit as $12$

$14-$ needs data value produced by $13$

$15-$ needs the same function unit as $14$

The pipeline diagram when the code runs on a $1-$way IOI$-$IOC

Draw the pipeline diagram when the code runs on the following multiple issue implementations:

a$.1-$way OOI$-$OOC

b$.2-$way OOI$-$OOC

c$.4-$way IOI$-$IOC

d$.4-$way IOI$-$OOC

e$.4-$way OOI$-$OOC