Assume as before that a single-cycle implementation takes 400 ps per instruction and that a 5-stage pipeline completes one instruction each 50 ps. IF HID EX MEM WB IF: Instruction fetch ID: Instruction decode and register read EX: Execute, address generation MEM: Memory access WB: Write back to registers How long does it take to execute a program with 1000 instructions in each case? What is the speedup of the pipelining implementation