Assume each word is 4 bytes.

Assume a cache with 2 blocks, each of size 16 bytes. The cache is provided a sequence of loads on the specified addresses. For each address, note whether it is a (H)it or a (M)iss. a) Direct-mapped, with the 5th least significant bit (the bit in the 16 position) determining where the address should be mapped Addresses 0x1A 0x3A 0x30OxlA0x240x14 0x300x28 Hit/Miss b) Fully associative using the least recently used (LRU) heuristic. Addresses 0x1A 0x3,A Hit/Miss 0x30x1A 0x24 0x14 0x30 0x28 Assume a cache with 2 blocks, each of size 16 bytes. The cache is provided a sequence of loads on the specified addresses. For each address, note whether it is a (H)it or a (M)iss. a) Direct-mapped, with the 5th least significant bit (the bit in the 16 position) determining where the address should be mapped Addresses 0x1A 0x3A 0x30OxlA0x240x14 0x300x28 Hit/Miss b) Fully associative using the least recently used (LRU) heuristic. Addresses 0x1A 0x3,A Hit/Miss 0x30x1A 0x24 0x14 0x30 0x28