Question: Assume that a byte addressable RAM is used and machine codes of an instruction set are of variable lengths, i.e., from 1 byte to 8

Assume that a byte addressable RAM is used and machine codes of an instruction set are of variable lengths, i.e., from 1 byte to 8 bytes, how would be keep/maintain sequence of instruction in a CPU, explain in detail with suitable diagrams and design procedure.

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