Assume that for INTx the priority increases with $x,$ which means INT$3$ has a higher priority than INT$1.$ If three enabled maskable interrupts are triggered with order INT$1$ INT$2($ISR$1$ is still running$)-->$ INT$3($ISR$1$ is still running$),$ the ISRx is executed with the order

ISR$1$ ISR$2$ ISR$3$

ISR$1-->$ ISR$2($ISR$1$ paused$)-->$ ISR$3($ISR$1$ and $2$ paused$)-->$ ISR$2($ISR$1$ paused$)-->$ ISR$1$

ISR$1$ IS$3-$ ISR$2$